As an example of a parallel computer system, there is known an SIMD (Single Instruction Multiple Data) parallel computer system that is used for image processing of video signals, for example.
As a related technique of such SIMD parallel computer system, there is Non-Patent Document shown below, for example.
In the SIMD parallel computer system presented in Non-Patent Document 1, each processing element (PE) is coupled in a ring form by a coupling line, and each PE is SIMD-controlled by a control processor (CP). With this SIMD control, each processing element (PE) applies an instruction issued by the control processor to data on its local memory so as to implement parallel processing by a plurality of processing elements (PE).
Further, as shown in FIG. 16, Non-Patent Document 1 also discloses a structure which performs memory transfer with an external memory via a line buffer by having data (one line) that is over a block of memories (RAMs) of the entire processing elements (PE) as a unit.
In the meantime, as another example of the parallel computer system, there is known an MIMD (Multiple Instruction Multiple Data) parallel computer system in which each of a plurality of processors processes different data independently. As an example of a related technique of the MIMD parallel computer system, there is Patent Document 1 shown below, for example.
As a method directed to the MIMD parallel computer system, Patent Document 1 discloses a structure in which values indicating data amount are exchanged with each other among the processors in parallel, scheduling by a prescribed simulation is executed in parallel by each of the processors, and the data is transmitted and redistributed among the processors based on the result of the scheduling.
Further, in Patent Document 1, a single processor includes a CPU and communication processors CM1-CML which perform transmission and reception with neighboring L-pieces of processors for performing scheduling by the prescribed simulation. Furthermore, the communication processors CM1-CML are connected to the neighboring processors via L-pieces of channels (communication paths).
Non-Patent Document 1: Shorin KYO, “A Video Recognition Processor for Intelligent Cruise Control Based on 128 4-Way VLIW RISC Processing Elements” IEICE Technical Report, ICD, May, 2003, Vol. 103, No. 89, pp. 19-24
Patent Document 1: Japanese Unexamined patent Publication Sho 63-147257